The Digital Radio Frequency (DigRF) protocol or standard specifies a digital serial interface, which replaces the analog interface in previous generation mobile handset architectures. The DigRF standard supports a variety of 3GPP air standards. The physical layer of DigRF standard connects a radio frequency integrated circuit (RFIC) and a base band integrated circuit (BBIC) via an interface. RFIC and BBIC may be configured as Application Specific Integrated Circuits (ASIC). Independent transmit (Tx) and receive (Rx) differential signal pairs allow for concurrent bi-directional communication between an RFIC and a BBIC.
Many platforms for mobile devices consist of two ASICs regarding the access part of the platform, namely the RFIC, which is responsible for converting the signal from base band to an analog RF signal and vice versa and the BBIC which contains the signal processing for providing a standard conform signal to the transmitting part of the RFIC or receiving a noisy signal and reconstruct the transmitted signal as accurate as possible.
To avoid mixed signal processing in the base band an often used approach is to use a digital interface between RFIC and BBIC with a minimized number of pins due to the fact that especially the RFIC package size is driven by pin count.
The most common standard for a digital interface between RFIC and BBIC is the DigRF standard specified by the Mobile Industry Processor Interface (MIPI) Alliance. This standard is available in version v3.09—in the following called DigRF v3 and in the latest version 4—in the following called DigRF v4. The interface is based on a serial high speed transmission over differential lines.
There could be proprietary solutions for digital interfaces between RFIC and BBIC, which face the same general characteristics which affect the platform design, which are especially:                Reference clock generation, controlling and distribution within platform        Functional split regarding real-time control, time accurate controlling of the RFIC and the BBIC and synchronization with respect to timing        Functional split between RFIC and BBIC regarding data processing, control loops and real-time control        
The first two items will be explained below in more detail.
FIG. 5 shows a conventional communication device 500 which comprises a radio frequency integrated circuit (RFIC) 502 and a base band integrated circuit (BBIC) 504. A digital radio frequency interface 506, 508 couples the RFIC 502 with the BBIC 504. A central processing unit (CPU) 510 is provided in the RFIC 502 which exchanges messages with the digital radio frequency interface 506. Furthermore, the CPU 510 may communicate with a timing generation unit 512 of the RFIC 502 for generating timing information or timing signals for time control of the RFIC 502. A clock generation unit 514, denoted as DCXO, generates a clock signal which can be transmitted to the BBIC 504.
The BBIC 504 also has a timing generation unit 516 which is communicatively coupled with the digital radio frequency interface 508 as well as with a physical layer (implemented in software) 518.
As can be taken from FIG. 5, each of the RFIC 502 and the BBIC 504 generates separately timing information in the corresponding timing generation unit 512, 516. In order to synchronize the RFIC 502 with the BBIC 504, Time Accurate Strobe (TAS) messages 520 with a high requirement regarding timing accuracy have to be exchanged within the communication device 500.
FIG. 5 also shows an analog-to-digital converter 522 for converting of incoming analog signals into digital signals. Furthermore, a digital-to-analog converter 524 is capable of converting digital signals for transmission into analog signals.
FIG. 6 shows a timing diagram 600 relating to FIG. 5 and illustrating schematically various messages to be transmitted over the various transmission lines shown in FIG. 5 and FIG. 6.
In the shown conventional approach, particularly the necessity of sending TAS messages 520 is problematic since these TAS messages 520 have to be very accurate in time and require significant effort.
According to the architecture of FIG. 5 and FIG. 6, real time tracking is split between BBIC 504 and RFIC 502. The timing generation unit 516 in the BBIC 504 is a hardware unit including at least a timer which reflects the timing of a serving cell. The RFIC 502 also has the timing generation unit 512 as a timer, whereas the DigRF standard defined TAS messages 520 are used for synchronizing the timing generation unit 512 (RFIC timer) to the timing generation unit 516 (BBIC timer).
The reference clock is generated in the RFIC 502. This is also reflected in the DigRF standards by specifying a RefClk signal as part of the standard. RFIC 502 normally offers several reference clock ports which can be used for different clients like BBIC 504, WLAN, Bluetooth, GPS or A-GPS.
There are in general two possibilities for delivering the reference clock to the rest of the platform:                Corrected reference clock: This means the clock is synchronized to the serving cell using automatic frequency correction. For other applications this may be a disadvantage.        Uncorrected clock: A free-running reference clock is delivered to BBIC 504. There is no control loop for the clock needed what eases design. The disadvantage is that the timing generation in BBIC 504 needs a correction mechanism to synchronize its real-time unit to the serving cell.        
In general, two different time domains can be distinguished:                The Real-Time is the time when a certain signal or part of a signal is received or transmitted as analog physical signal on a reference point, for instance antenna or ADC input respectively DAC output.        The Sample Time is the time instance at which a sample arrives at BBIC 504 or RFIC 502. This time has in average a constant relation to the real time but may strongly jitter with short-term perspective.        
Another important aspect is the memory location of samples in BBIC 504, because this gives a direct connection to the real-time. The BBIC 504 needs a reference point, which means that the BBIC 504 needs to know the real time instance of one sample stored at a specific memory location (see FIG. 6). With this knowledge all other real-time instances for all other samples can be calculated making use of the fact that the samples are equidistantly sampled.
In the following, real-time control in the conventional system will be explained.
In conventional platforms using DigRF v3 or DigRF v4 the functional split between BBIC 504 and RFIC 502 is not very clean regarding real-time controlling. The real-time control is spread over BBIC 504 and RFIC 502, whereas the master is the BBIC 504.
This real-time information is mainly used for radio control issues and for sending periodical events to the software, which is planning then the next processing steps. It is also used for controlling sleep modes and wake up.
The radio controlling itself shall be done highly accurate because this directly affects system performance with respect of throughput.
The software events are anyway caught by a processor which cannot react very accurately due to context switch, etc.
The RFIC 502 includes either no internal timer (not shown in FIG. 5) which means that all detailed control must be handled by the BBIC 504, or the RFIC 502 includes an additional timing generation unit 512 (scenario of FIG. 5) which cares about detailed sequences done within the RFIC 502. In the latter case there is a rough real time control which is done by BBIC 504 and a fine real-time control which is done by RFIC 502 autonomously. Both approaches require time accurate signaling between RFIC 502 and BBIC 504.
The DigRF interfaces 506, 508 could contain sample based counters which count incoming or outgoing samples. Based on this counters, events may be triggered towards software or hardware components for data flow control or raising control events. These events have a loose coupling to the counter of the timing generation unit 516, because in average the number of samples delivered over the DigRF interfaces 506, 508 is proportional to the counter of the timing generation unit 516, but due to the packet based delivery over the DigRF interfaces 506, 508 and the multiplexing with other messages there is a certain jitter within the sample counters.
To synchronize the BBIC 504 real time control block to the RFIC 502 real time control parts highly accurate strobe messages are needed. In conventional analog interfaces these are dedicated lines, in DigRF based systems these are the TAS messages 520. In the latter one the accuracy is limited to around 30 ns, and the TAS messages 520 cause additional design effort.
Concluding, the described existing solutions suffer from shortcomings.
The BBIC 504 has the timing generation unit 516 as master timer unit, which maintains a timing of a serving cell and neighbored cells in connected mode and a special timer for sleep mode handling. To follow a timing of a serving cell, timing has to be synchronized to evolved NodeB (eNodeB) using automatic frequency control (AFC). This requires AFC to correct a reference clock or to control a mechanism which controls the real-time block in BBIC 504.